Software Engineer III, TPU Performance, Hardware and Software Codesign

Overview In this role you will bridge ML workloads and TPU hardware to optimize performance at scale. You’ll help define benchmarking, characterization, and compiler-aware tooling to enable fast grounding-to-silicon and efficient TPU mappings. You will collaborate with product teams to onboard new workloads and drive TPU adoption through measurable improvements in performance and efficiency. Your work will shape roadmaps and influence leadership discussions on ML infrastructure and accelerator design. Compensation / Benefitsbonus targetequitybenefits ResponsibilitiesDevelop benchmarking and workload characterization strategies to enable rapid silicon grounding and root-cause performance analysisDrive full-stack hardware-software co-design to optimize current and future ML accelerator architectures for production modelsPartner with Product Areas (e.g., YouTube and Ads) to scale key workload pipelines efficiently during TPU Pilot and GA transitionsBuild and upgrade compiler-aware simulator tools, hardware cost-models, and performance-ladder pathways to baseline and project silicon capabilitiesDistill complex performance analyses and hardware trade-offs into presentations to guide TPU roadmap decisions in leadership forums Key requirementsBachelor’s degree or equivalent practical experience2 years of software development experience in one or more programming languages2 years of experience with performance, large-scale systems data analysis, visualization tools, or debugging2 years of experience with computer architecture, performance analysis, and performance modelingcollaborationleadershipcommunicationperformance analysishardware-software co-designcompiler architectures (XLA)