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Experience with Python, Perl, Tcl, and shell scripts 4+ years of experience in RTL design using Verilog, SystemVerilog Experience in synthesis, timing closure for FPGA and/or ASICs Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs. BSEE or MSEE, with experience in ASIC development and/or FPGA prototyping Ability to work independently, and proactively identify and resolve issues.
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Depending on role, prior experience or knowledge requirements could include programming skills and technologies such as: Verilog, SystemVerilog , VHDL, Perl, TCL, C, C. Working with other engineering team members to gather requirements and build solutions to achieve design targets and specifications, which may include developing scripts to help aggregate and analyze data from multiple third-party tools.
Full-timeExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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Experience in a scripting language (Python, Perl, or Tcl) and a hardware description language (Verilog or VHDL) As a Logic Synthesis domain expert, you will research, invent, and implement robust software solutions for RTL synthesis, mapping, and inference; P&R-based physical synthesis and timing-driven re-optimization while leveraging unique features of the Achronix FPGA technology.
$110,000 - $160,000 a yearFull-timeExpandApply NowActive JobUpdated 7 days ago - UpvoteDownvoteShare Job
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Supermicro is a Top Tier provider of advanced server, storage, and networking solutions for Data Center, Cloud Computing, Enterprise IT, Hadoop/ Big Data, Hyperscale, HPC and IoT/Embedded customers worldwide.
$107,000 - $171,000 a yearExpandApply NowActive JobUpdated 14 days ago - UpvoteDownvoteShare Job
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Strong knowledge of DFT methodologies, industrial standards, and practices Strong working knowledge of Chip design, Verilog/System Verilog, and design verification Experience with STA tools like Primetime, SDF generation and Gate-level simulations Understanding and expert handling of Verilog HDL based Netlists, design libraries and Scripting (Perl/Tcl) Why is This a Great Opportunity: Outstanding technology.
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We're looking for Senior ASIC Digital Design Manager to join Synopsys Solutions Group, Digital IP Subsystems Team in Sunnyvale, ca. Programming skills such as System Verilog, TCL, Perl or Python.
$110,000 - $194,000 a yearFull-timeExpandApply NowActive JobUpdated 13 days ago - UpvoteDownvoteShare Job
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Programming skills in Python, Perl, Ansible, Terraform and Shell scripting. The Engineering team develop innovative solutions that are transforming the internet security business, and millions of users rely on our service for data protection and comprehensive security.
$178,500 - $210,000 a yearFull-timeExpandApply NowActive JobUpdated 17 days ago - UpvoteDownvoteShare Job
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Synthesis/P&R/Physical Design: Deep expertise in understanding Digital implementation engine issues and providing quick solutions (usually TCL/Perl prototypes) to show that EDA engines can be extended to meet the Foundry/customer’s needs.
$157,000 - $235,000 a yearFull-timeExpandApply NowActive JobUpdated 25 days ago - UpvoteDownvoteShare Job
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Proficient in batch/bash/shell/Perl/HTML/PHP/Python/C/C. Super Micro Computer, Inc. is currently seeking a Senior System Validation Manager to supervision Validation team in Server Production. Proficient in batch/bash/shell/Perl/HTML/PHP/Python/C/C.
$152,000 - $218,000 a yearFull-timeExpandApply NowActive JobUpdated 3 months ago - UpvoteDownvoteShare Job
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Develop, lead, perl, senior, senior software developer, senior software engineer, software engineer lead. We are committed to collaborating with stakeholders in the industry to develop and implement viable, alternative solutions in a way that protects the privacy of users while also ensuring the continued vitality of the web.
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As a team member of the Methodology Design team, you will be involved with all aspects of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Provide innovative solutions to customize and improve quality and efficiency of mixed-signal design.
ExpandApply NowActive JobUpdated 14 days ago - UpvoteDownvoteShare Job
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Deep understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers, PLLs. Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions.
$180,000 - $345,000 a yearFull-timeExpandApply NowActive JobUpdated 2 months ago - UpvoteDownvoteShare Job
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Coding for benchmark code development/modificationBS in Electrical Engineering or equivalent experiencePREFERRED QUALIFICATIONS:Experience with embedded CPU/DSP such as ARM, TI, Tensilica or Hexagon DSPExperience with Lotherbuch debugger probe, NIDAQ Data acquisition equipmentMatlab, Python, Perl (or similar) scripting and data-post-processing toolsExcel for model fitting, data visualization and analysisDiagnostic code development in C/C.
$90 - $120 an hourExpandApply NowActive JobUpdated 3 days ago - UpvoteDownvoteShare Job
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SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Skype, OneDrive and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions.
$94,300 - $182,600 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Going far beyond the standard call center or tiered support position, the Technical Solutions Engineer at Arista Networks is a top level engineer, equivalent to a Tier 3 or Escalation Engineer in most support organizations.
$90,000 - $170,000 a yearExpandApply NowActive JobUpdated Today
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