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In the BMS Verification Engineer role, you will verify that Archer’s high voltage battery management and charging systems satisfy their requirements – enabling the use of electric vertical-takeoff-and-landing aircraft for urban air mobility.
ExpandApply NowActive JobUpdated 12 days ago - UpvoteDownvoteShare Job
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ASIC verification using UVM/System Verilog. 12+ years ASIC design verification experience and collaborate closely with verification engineers, designers, hardware & cross functional teams to verify the ASIC in simulation, in emulation and during ASIC bring up.
ExpandApply NowActive JobUpdated 6 days ago - UpvoteDownvoteShare Job
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Significant Experience with standard ASIC Verification flow/software tools. Define verification plan in co-ordination with Architects, Logic and Mixed-signal designers. As aPrincipal Verification Engineer, the candidate will be reporting to the Director of Design Engineeringand is a Full-Time position.
$129,300 - $240,100 a yearFull-timeExpandApply NowActive JobUpdated 9 days ago - UpvoteDownvoteShare Job
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Experience with DO-178C software verification and ARP4754 development process. Working knowledge of lithium-ion battery electrochemistry and electrothermal models. Experience with high voltage battery systems.
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We are seeking a highly experienced ASIC Design Verification Engineer to join our dynamic team. The ideal candidate should have a strong background in ASIC design verification, test planning, UVM, and scripting, with a passion for driving innovation and change in the industry.
ExpandApply NowActive JobUpdated 7 days ago - UpvoteDownvoteShare Job
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Design and implement test cases for the 4G/5G firmware verification on Test equipments like Keysight, R&S and Anritsu. Assist in the development of pre-silicon emulation systems/virtual platforms anduse them for pre-silicon firmware design verification.
ExpandApply NowActive JobUpdated 11 days ago - UpvoteDownvoteShare Job
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Senior ASIC Verification Engineer- System Verilog / UVM. We are partnered up with a well-established Semiconductor organisation who enable state of the art perception for autonomous vehicles who are looking for Senior ASIC Verification Engineer to join their team in California.
ExpandApply NowActive JobUpdated 8 days ago - UpvoteDownvoteShare Job
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Intel and/or external foundry process technology knowledge in advance nodes- Industry direct experience to support customers in Asic/Physical Design and/or Physical Verification/runsets, in terms of technology, or EDA tools.
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The Role: The Infinity Fabric transport layer verification team is looking for a senior pre-silicon verification engineer to help verify our configurable switches and die-to-die interconnect.
Full-timeExpandApply NowActive JobUpdated 6 days ago - UpvoteDownvoteShare Job
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Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation.
$150,000 - $180,000 a yearFull-timeExpandApply NowActive JobUpdated 12 days ago - UpvoteDownvoteShare Job
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This young and ambitious AI company are currently seeking a Senior ASIC Verification Engineer to be responsible for the pre-silicon correctness and quality of a high-performance and low-power convolutional neural network accelerator ASIC.
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Founded in 2000, we specialize in solving the toughest functional verification problems for ASIC, FPGA and independent IP development. Verilab Design Verification Engineer San Jose, CA - Full Time Job SummaryWe invite you to join our highly motivated team of consultants, providing clients with the very best in verification.
Full-timeExpandApply NowActive JobUpdated 6 days ago - UpvoteDownvoteShare Job
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Define/Create a scalable constrained-random verification environment using SystemVerilog and UVM.Drive stimulus, comprehensive coverage strategy to show continuous progress towards tape-out. We are now looking for a Senior Design Verification Engineer.
$156,000 - $287,500 a yearFull-timeExpandApply NowActive JobUpdated 6 days ago - UpvoteDownvoteShare Job
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Strong experience developing complex/random verification environments using System Verilog/UVM/OVM. Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology.
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Join our team of verification experts in San Jose, CA to verify the next generation of RISC-V based Systems on a Chip (SOC) semiconductor products integrated into state of art FPGA architectures.
Full-timeExpandApply NowActive JobUpdated 7 days ago
Title: insurance verification Company: Working Solutions in San Jose, CA
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