DFT Engineer

Overview In this role you will own testability architectures and DFT logic across the full hardware lifecycle, shaping testability for complex SoCs. You will work closely with design and verification teams to integrate robust DFT solutions that enable reliable tapeouts. The role combines RTL design, verification, and DFT specialization to drive scalable, high-quality silicon. This is an opportunity to contribute to cutting-edge semiconductor platforms powering AWS infrastructure. ResponsibilitiesDefine and implement DFT architectures for complex SoCsDevelop and integrate DFT logic including MBIST, JTAG/TAP, and boundary scanRTL coding and debug of DFT controllers and infrastructure using Verilog/SystemVerilogDrive gate-level simulations to validate DFT functionality and test patternsDevelop and verify DFT logic using UVM-based testbenches, functional simulation, and coverage-driven verificationParticipate in design reviews, DFT sign-off processes, and tapeout preparationCross-functional collaboration with Design, Verification, Physical Design, and Production/Test teams Key requirementsBSc in Electrical Engineering, Computer Engineering, or Computer Science2+ years of hands-on RTL design experience using Verilog/SystemVerilogExperience with DFT design and implementation (MBIST, JTAG/IEEE 1149.1) and familiarity with Synopsys DFT Compiler and TessentExperience with chip design flows and gate-level simulationsVerification background including UVM testbenches, coverage-driven verification, FPGA and emulator environments, with scripting in Perl, Tcl, and/or PythonEnd-to-end chip development experience from RTL through synthesis, timing analysis, and physical design constraints to post-silicon validation, production, and memory fault debuggingCross-functional collaborationTeamworkContinuous learningDFT design and implementation (MBIST, JTAG/IEEE 1149.1)Memory repair flowsVerilog/SystemVerilog RTL coding