Senior R&D IC Design Verification Engineer (up to $300k)

Role: Senior R&D Design Verification EngineerComp: Total first year comp up to $300k! Base (up to 160k) + bonus (20%) plus very generous RSUs!Location: San Jose, CA (Onsite)Position OverviewWe are seeking a highly skilled R&D Engineer specializing in IC Design Verification to join our innovative team. The ideal candidate will be responsible for the design verification of complex integrated circuits, ensuring high-quality performance and functionality.Top Reasons To Work With UsLow stress environment with great work/life balanceAmazing package with base, strong bonus and industry leading RSU program!Work for an industry leader developing chips for the latest in AIKey ResponsibilitiesThe engineer will oversee the verification of intricate switch designs. Duties will encompass developing SystemVerilog-based verification setups (including testbenches, checkers, and transactors) and formulating and implementing test plans for verifying RTL and gatesim-based designs at both the block and chip levels. Additionally, the engineer will be responsible for generating ATE testing vectors and creating C-based diagnostic tests to be executed on the actual silicon.Qualifications RequiredMasters plus 4 yrs or Bachelors plus 6 yrs relevant experienceStrong design verification for complex designs at the chip and/or block levelUVM, Verilog, SystemVerilogSOC strongly nice to haveBenefitsGenerous package including:Unlimited PTO policyMedical, Dental & Vision401k with company match up to 6%Annual bonus (varies based on your level)VERY generous stocks (RSUs)Relocation bonus