FPGA Digital Design & Verification - Intern

Job Details:Job Description:Altera is seeking a highly motivated Graduate Intern to join our FPGA Digital Design and Verification team. This internship provides hands-on experience working on industry-leading programmable logic devices, SoC platforms, and verification environments. The role is ideal for graduate students eager to grow their expertise in SystemVerilog, UVM-based verification, and digital design methodologies.You will collaborate with experienced engineers to design, verify, and validate RTL blocks and system-level features used in next-generation FPGA products.Key ResponsibilitiesDevelop and maintain SystemVerilog/UVM-based verification environments for FPGA IPs and subsystemsCreate self-checking testbenches, constrained-random tests, and functional coverage modelsWrite and debug SystemVerilog Assertions (SVA) to ensure protocol and design correctnessExecute and analyze simulations using industry-standard EDA tools (VCS, QuestaSim, ModelSim)Assist in debugging RTL and verification failures, working closely with design engineersVerify common communication protocols (e.g., UART, SPI) and custom interconnectsContribute to documentation of verification plans, test strategies, and resultsSupport FPGA-based systems including AI/ML accelerators, memory interfaces, and SoC componentsThe pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.$95K - $100K USDWe use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.Qualifications:Required QualificationsCurrently pursuing a Graduate Degree in Computer or Electrical Engineering or related fieldStrong foundation in Digital Logic Design and Computer ArchitectureProficiency in SystemVerilog and VerilogKnowledge of UVM, functional coverage, constrained random verification, and assertionsExperience using simulation and verification tools such as ModelSim, QuestaSim, or Synopsys VCSFamiliarity with Linux-based development environmentsAbility to debug simulation issues and analyze waveforms effectivelyPreferred QualificationsHands-on project experience with UVM-based verification environmentsExperience verifying communication protocols (UART, SPI, AXI preferred)Exposure to FPGA tools such as Intel Quartus Prime or Xilinx VivadoKnowledge of SVA or formal verification conceptsProgramming or scripting experience in Python, Perl, Tcl, or CExposure to HLS, SoC design, or hardware acceleration for AI/ML workloadsJob Type:Student / Intern (Fixed Term)Shift:Shift 1 (United States of America)Primary Location:San Jose, California, United StatesAdditional Locations:Posting Statement: