Senior FPGA Design Engineer

Job Description Job Title: Senior FPGA Engineer IIIDepartment: Engineering->Platforms->FPGA SoC GroupReports To: Director, PlatformsFLSA Status: ExemptLast Modified: 9/10/2025Level: T3Location Chandler, AZ – Onsite 5 Days a weekCompany OverviewComtech Telecommunications Corp. is a leading global technology company providing terrestrial and wireless network solutions, next-generation 9-1-1 emergency services, satellite and space communications technologies, and cloud-native capabilities to commercial and government customers around the world. Our unique culture of innovation and employee empowerment unleashes a relentless passion for customer success. With multiple facilities located in technology corridors throughout the United States and around the world, Comtech leverages our global presence, technology leadership, and decades of experience to create the world's most innovative communications solutions. For more information, please visit www.comtech.com.We're seeking curious, growth-minded thinkers to help shape our vision, structures, and systems; playing a key role as we launch into our ambitious future. If you're invigorated by our mission, values, and drive to change the world — we'd love to have you apply.Position SummarySenior FPGA Designer with experience in the entire design flow for complex FPGA's.ResponsibilitiesDesign, develop, document, debug and test FPGA SoC systems; including:IP Integration into FPGA Projects (synthesis/implementation)High-Performance FPGA IP (VHDL/SystemVerilog)Userspace Drivers for FPGA IP (C++)Firmware for Embedded Microcontrollers (C)Utilize strong communication skills to effectively work and communicate with team members and engineering management.QualificationsStrong digital design engineer with FPGA/ASIC SoC design experienceStrong FPGA Implementation with Altera Quartus or Xilinx VivadoExperience designing/debugging SoC systems with AMBA-compliant AXI and APB interfacesExperience designing fmax-optimized, high-throughput, pipelined AXI-Stream IPCapable of creating RTL simulations to identify and resolve most issues before hardware testsKnowledgeable in Static Timing Analysis (STA) and Synopsis Design Constraints (SDC)Experience analyzing STA reports and post-synth netlist/placement to resolve failing pathsExperience contributing to schematic capture and layout for FPGA portions of PCB designsExperience implementing at least one Gigabit Transceiver Protocol:PCI Express, Interlaken, USB SuperSpeed1000BASE-X/SGMII, 10GBASE-R, 40GBASE-4, 100GBASE-R4Experience implementing Network Protocols, such as:L1: IEEE 802.3, Cisco, Q/SFP+ MSA standards for Ethernet (1G to 100G)L2/L3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCPL4: VITA 49.2, IEEE-ISTO 4900 Digital IF Interoperability Standard (DIFI) and/or eCPRi(Highly Desired)Proficient in SW development with C, C++ and GIT version controlProficient in Microsoft Office Tools (Word, Excel, PowerPoint, Visio, etc.)Demonstrated experience supporting multi-disciplinary, cross functional and matrixed teamsDesired QualificationsWorking knowledge of digital IF streams such as VITA 49.2, DIFI and/or eCPRi (Highly Desired)Working knowledge of Embedded Linux: Kernel / Yocto / U-Boot / DeviceTreeWorking knowledge with SATCOM waveforms like DVB-S2X and/or 5G NTN 3GPP Rel 17/18Working knowledge of communication networks and security within a zero-trust environmentExperience with Partial Reconfiguration/DFX or PCIe CvPPossess an active DoD clearance or demonstrate readiness to obtain oneEducationBachelors in Electrical or Computer Engineering (or related degree).Experience:5+ years of FPGA/ASIC SoC design experience.Comtech Telecommunications Corp. is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability protected veteran status or other characteristics protected by law.