Field-Programmable Gate Arrays Engineer

Mandatory: Fusion Complier and Strong Scripting experience • Strong expertise along-with complex SoC/IP debug is must • At-least 5+ years of experience in System Verilog HVL and C/C++. • AMBA AXI bus along-with ARM or C based processor • Bi-frost/Processor based C and SV/UVM mix Verification. • Experience in complete verification cycle which includes development of test plan, • BFM/Driver/Monitor/Scoreboard component development and integration in test bench, • stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. • Make/Perl/Python At-least 5+ years of experience in Verilog Design • AMBA AXI bus along-with ARM or C based processor • Ensure customer satisfaction. • Reporting to customers on daily or weekly progress effectively