ASIC & FPGA Design Engineer Sr - E3

Overview As an FPGA Design Engineer in the ASIC/FPGA department, you lead digital development for missile platforms, turning MATLAB/Simulink models into efficient RTL and integrating onto AMD RFSoC and Versal devices. You collaborate with algorithm, software, and hardware teams to deliver high-performance, mission-critical FPGA solutions. You will drive design, verification, and hardware bring-up, shaping the digital architecture for next-generation defense systems. This role offers impact at scale within a multidisciplinary organization that values growth, collaboration, and technical excellence. Compensation / BenefitsMedical, Dental, VisionFlexible work arrangements (e.g., 4x10)401(k) matchPaid time off, holidays, parental leaveEAPFlexible Spending Accounts (FSA) ResponsibilitiesDevelop complex FPGA designs from spec through implementationSupport requirements capture, architecture, and detailed FPGA design for devicesPerform functional simulation, timing closure, and hardware bring-up/debugPlan and execute FPGA verification including testbench, coverage, and regression testingSupport integration with hardware and processor-side softwareDocument designs and verification per release processesCollaborate with circuit card design, software, and systems engineering teams Key requirementsB.S. or M.S. in Electrical/Computer Engineering or related fieldProficiency in VHDL, Verilog, or SystemVerilogExperience with FPGA simulation tools such as Synopsys VCSProficiency with timing analysis, clock-domain crossing, and IP integrationExperience with AMD/Xilinx UltraScale+ FPGAs and VivadoStrong understanding of digital design principles, timing analysis, CCC, and signal integrityExperience high speed data and memory interface implementationLeadership experience mentoring engineers or leading design reviewsIndependent and collaborative work style within a multidisciplinary hardware teamStrong debugging and problem-solving abilitiesSimulink/MATLAB model to synthesizable code using Vivado HLSExperience with AMD RFSoC and Versal familiesExperience with MFC DAR process