DFT Engineer

Job DescriptionBelow JD for a DFT engineer and panel details. Please let me know if you need additional details.Location: Santa Clara, California.NVIDIA has relaxed the JD, and ATPG experience is not mandatory for candidates to submit going forward.More of the DFx skills and other DFT skills are required.Job details:-Familiarity with the Siemens suite of DFT toolsDFT insertion for SCAN (with SSN) and MBISTMBIST Repair Implementation and VerificationGenerating collaterals for Test Timing and Place and RouteExpertise in IJTAG 1687 standard and good at understanding ICL and PDL standard SpecVerification of DFT features, including· Boundary Scan· JTAG· SCAN· MBIST· High Speed IO