Lead Physical Design Engineer

Efficient is developing the world's most energy-efficient general-purpose computer processor. Efficient's patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform's unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolutionEfficient's Lead Physical Design Engineer will design and implement our chip through tape-out. If you are an engineer who wants to be part of an intensely skilled team and wants to have an immediate impact on the design and implementation of our chip, this is for you! We seek individuals to leverage low-power techniques and design-technology co-optimization in advanced technology nodes to build energy-efficient SoCs.This is a unique opportunity to get in at the ground level and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!Key ResponsibilitiesLead physical design team from synthesis to sign-off and tape-outRun physical design tasks including synthesis and place-and-routeWork with digital design team to integrate analog and digital IP into designInteract with design verification team and run verification tasks on designResolve DRC & LVS violations to produce DRC-clean GDS-II of chip to deliver to foundryInteract with foundry partners through multi-party wafer and manufacturing runsInteract with backend services partners on physical design tasks through sign-offImplement and execute physical design management process with PD teamSetup and maintain physical design tools, primarily Synopsys, but also potentially including Mentor/Siemens EDA, Cadence, or ANSYS tools as necessaryRun power and energy modeling on synthesized, place-and-routed designInteract with digital design team to resolve RTL-level issues leading to DRC violationsMentor and train junior hardware physical design engineersRequired Qualifications & Experience RequirementsMust be an outstanding leader in physical design with substantial experience successfully bringing real chips from design to tape-out.Master's degree in Electrical Engineering with 7+ years of industry experience or PhD in Electrical Engineering with 5+ years of industry experience.Experience running physical design tasks using Synopsys and/or Cadence EDA tools.Experience interacting with chip foundry services companies.Experience integrating analog and digital IP into prior tape-outsExperience with post-silicon bring-up and working with post-silicon validation teamExperience with performing verification and interacting with verification and design teamsExperience with power and energy modelingExperience with continuous integration and testingStrong attention to detail, good work ethic, ability to work on multiple projects simultaneously, and good communication skillsWe offer a competitive salary for this role, generally ranging from $200,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.Why Join Efficient?