Technical Program Manager, Silicon/Hardware

Overview In this role you will own end-to-end silicon hardware programs, from concept to tapeout, coordinating cross‑functional teams to deliver high-performance, reliable GenAI silicon. You will drive milestones, risk management, and phase-gate reviews while partnering with architecture, RTL design, and verification. This position merges hardware engineering leadership with strategic program management to scale silicon development. You will work closely with leadership to provide clear updates and drive critical tapeout readiness and silicon bring-up. A meaningful hook is the opportunity to shape next‑gen silicon for a compute platform aimed at AGI. Compensation / Benefits4 weeks PTO + 12 holidayshealth, dental, vision insurance and life insuranceretirement plan with company contributionprofessional development budgetAI resources stipendremote work options and commuting reimbursement ResponsibilitiesLead end-to-end silicon HW programs from concept to production across cross-functional teamsCollaborate with Architecture, RTL Design, and DV to identify bottlenecks and mitigate risks before tapeoutDefine and refine HW stage-gate processes for smooth transitions from architecture to implementation and verificationDevelop program management playbooks and best practices for cross-functional deliveriesSupport silicon planning across performance, power, area, cost, reliability, and manufacturability tradeoffsTrack dependencies, risks, milestones, tapeout readiness, and escalation pathsManage technical risks across schedule, design maturity, IP readiness, verification, signoff, and supply chainAct as liaison to leadership with clear, timely updates and insights Key requirements15+ years in chip/IC development in engineering, management, or TPM roles; at least 3 years in a TPM roleExperience driving silicon HW programs through multiple lifecycle phases with end-to-end executionProven ability to lead complex cross-functional programs involving multiple teams, vendors, and tight schedulesTechnical fluency in SoC or chiplet design flows and related milestones without translationStrong judgment to balance performance, power, area, cost, schedule, quality, and riskAbility to drive schedules, dependency management, risk management, milestone governance, and executive communicationExperience coordinating design reviews and driving closure across teamsStrong written and verbal communication skills to summarize risks, tradeoffs, decisions, and schedule impactProficiency with program-management and collaboration tools such as Jira, GitHub, Confluence, Smartsheet, MS Project, Google Workspacecross-functional collaborationclear written and verbal communicationrisk management and problem-solvingSoC or chiplet design flowsRTL milestones, DV signoff, silicon bring-upstage-gate and tapeout processes