Technical Program Manager III, Memory Silicon Development, Technical Infrastructure
Overview:
As Silicon Development TPM, you drive the end-to-end planning, execution, and delivery of memory-focused silicon and hardware programs. You partner with SoC and cross-functional teams to shape schedules, manage risks, and optimize tradeoffs across technical, budgetary, and timeline dimensions. You lead data-driven milestones from concept to NPI, ensuring on-time delivery and readiness for manufacturing and sustaining support. This role connects engineering excellence with program discipline to advance Google's custom silicon for AI, ML, and storage acceleration. Compensation / Benefitsbonus targetequitybenefits
Responsibilities:
- Plan, justify, and coordinate custom silicon projects and development tooling from concept to deployment
- Generate task lists and schedules; build efficient timelines and track progress with team leads
- Lead credible, data-driven schedules and milestones; identify challenges and mitigations proactively
- Facilitate technical, budgetary, and schedule tradeoff discussions across cross-functional teams
- Manage execution and issue handling through design, development, test, manufacturing, deployment, and sustaining phases for silicon/hardware
- Coordinate memory-related aspects of silicon programs, including planning, validation, and early NPIWork with SoC subsystems and external vendors/IP to drive handoffs and align contract requirements
Key requirements:
- Bachelor's degree in a technical field; or equivalent practical experience 5 years of program management experience
- Experience working with SoC subsystems
- Experience managing memory-related silicon chip programs through all stages (concept, architecture, design, validation, physical design, silicon engineering, silicon validation, NPI)cross-functional collaborationstrong communication with executives and engineersrisk identification and mitigation
- SoC subsystemsmemory-related silicon programs (custom HBM, DDR, DRAM)vendor management and evaluation of memory technologies