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9+ years of experience in RTL design for ASIC and FPGA.Additional Preferred Qualifications:Experience in Git or GitHub revision control system. As a FPGA Silicon Design Engineer, you will be responsible for, but not limited to, the following:Develop the system model, algorithm, and subsystems for integration in full chip designs.
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Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Texas, AustinAdditional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Colorado, Fort Collins, US, Massachusetts, Hudson, US, Oregon, HillsboroBusiness group:In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products.
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Possess an in-depth understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios. Develops GPU validation methodologies, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis.
$91,500 - $137,436 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Guides Mid-level and Junior-level Enterprise architect contractors in the development of proposed changes to architecture design based on analysis of requirements and new technology. Required Skills and Experience: Active TS/SCI Clearance Bachelor's degree or higher in Computer Science, Information Technology, Management Information Systems, or related STEM degree program or equivalent Senior level experience as an Enterprise Architect.
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Digital Design: Create compelling visual content using tools like Canva or Figma to support marketing campaigns and social media initiatives. Proficiency in digital design tools such as Canva or Figma, with a portfolio demonstrating past projects.
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Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
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This includes collaboration with other team members to design and build a highly resilient Kubernetes container platform that is optimized for AI workloads on Intel accelerator hardware.
$186,552 - $279,772 a yearFull-timeExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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Logistics capabilities development in support of Factory Operations (e.g. Intel Fab, Assembly Test, Design Center, other). As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art.
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Hands-on experience with LRP process, Capacity Planning, Process design with a strong demonstration of customer-focused process development. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: Business group: As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.
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Collaborate across a variety of teams to enable our Data Platform needs and design, implement, and maintain a secure and scalable infrastructure platform spanning across AWS/Azure and our Data Center.
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We are the Intel CEG DDR Structural Design team driving the future of DDR technologies with Intel. The Physical Design Engineer drives integration of analog and mixed signal IPs and highspeed interfaces into subsystems or analog components and partners with package and platform teams on analog integration.
$144,501 - $217,311 a yearFull-timeExpandApply NowActive JobUpdated 2 days ago
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