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We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. + Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms.
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A minimum of 2 years of experience RTL Integration, 3rd Party IP RTL through Lint, CDC check, DFT check with spyglass or VC static and generate clean reports. Proficient with System Verilog/Verilog RTL source code.
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Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs. + Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, constraints, static timing analysis, formal verification, Gate level functional & timing ECO in advanced technology nodes.
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Port ASIC and IP RTL code to prototyping and emulation platforms ( Zebu/HAPSs, Palladium/Protium) + A minimum of 5 years of experience with porting ASIC/IP RTL to Emulation platforms: Zebu/HAPSs, Palladium/Protium.
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Reading and interpreting technical specs to come up with Micro-architecture and implement RTL design in System Verilog. DEG/IMSG is seeking an experienced IP Logic Design Engineer for its PCIe and Accelerator IP development organization, a dynamic team with a history of outstanding execution and industry-leading accomplishments.
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Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto. + In-depth knowledge of digital logic design, chip architecture and microarchitecture. Testbench development - System Verilog UVM and C tests.
ExpandApply NowActive JobUpdated 7 days ago - UpvoteDownvoteShare Job
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Experience logic designer in Verilog or VHDL and familiar with ASIC or FPGA EDA tools. Work with Research Groups, Platform Engineering teams at all layers of Hardware & Software - from FPGA BS to Firmware to OS (ESXi) to Hypervisors.
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Proficiency with ECO for functional and DFT timing closure. Deliver physical design of an end-to-end IP or integration of ASIC/SoC design. Accenture engineers are true Silicon to SW Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
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Familiar with constraint checking tools and techniques to deliver quality constraints for both pre and post CTS views. Experience with Python, TCL or Perl programming. If you would like to be considered for employment opportunities with Accenture and have accommodation needs for a disability or religious observance, please call us toll free at 1 (877) 889-9009, send us an email.
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Bachelors Degree or equivalent (12 years) work experience (If an, Associates Degree with 6 years of work experience) TCL, Python and/or Perl programming. Inclusion and diversity are fundamental to our culture and core values.
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A minimum of 3 years of experience RTL Integration, 3rd Party IP RTL through Lint, CDC check, DFT check with spyglass or VC static and generate clean reports. A minimum of 3 years of experience RTL Integration, 3rd Party IP RTL through Lint, CDC check, DFT check with spyglass or VC static and generate clean reports.
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Our rich diversity makes us more innovative and more creative, which helps us better serve our clients and our communities. We have an unwavering commitment to diversity with the aim that every one of our people has a full sense of belonging within our organization.
ExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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The ideal candidate can help along the design flow to establish synthesis runs with the related timing constraints, perform Lint, CDC, DFT checks, support regression and release process and analyze STA timing results.
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Familiar with setting up and debugging GLS runs. An experienced SoC Integration Engineer. Proficient with Synopsys Design Compiler and/or Design Compiler Ultra. If you would like to be considered for employment opportunities with Accenture and have accommodation needs for a disability or religious observance, please call us toll free at 1 (877) 889-9009, send us an email or speak with your recruiter.
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We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. Applicants for employment in the US must have work authorization that does not now or in the future require sponsorship of a visa for employment authorization in the United States.
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