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Timing Design Engineer
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$125 - $150
- We have an opportunity for a results-oriented and outstandingly hardworking Timing Design Engineer.
- In this role, you will be at the center of a PHY design effort collaborating with architecture, CAD, logic design teams, with a critical impact on delivering outstanding PHY designs.
- Confirmed knowledge of Basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixes
- As a Timing Design engineer you will be involved with all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block level static timing constraints.
- Close timing on critical blocks by working with RTL, PD teams.
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