Enfabrica

Join a world-class team of silicon and distributed systems experts at Enfabrica as a Package Design Engineering Lead. You have the opportunity to be part of building a groundbreaking new category of products that revolutionize the performance and scalability of next-generation AI and accelerated computing systems, and to help solve key infrastructure challenges facing our customers.. Package planning and integration with die, package, and PCB design teams.. Hands on large body size, high power, high speed substrate design using Cadence APD/SIP. Strong understanding of SI/PI, and mastery of Ansys HFSS and SiWave.. Target Companies: Cisco, Juniper, Google, Annapurna, Innovium, Mellanox/Nvidia, Broadcom, Barefoot, Intel, Fungible, Cavium/Xpliant, Marvell, Google, Cray, Mediatek/Nephos, Insieme, Nuova

design engineering

Summary
Join a world-class team of silicon and distributed systems experts at Enfabrica as a Package Design Engineering Lead. You have the opportunity to be part of building a groundbreaking new category of products that revolutionize the performance and scalability of next-generation AI and accelerated computing systems, and to help solve key infrastructure challenges facing our customers.
We are looking for talented, motivated engineers with experience in building high power, high speed, megascale networking and computing devices, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced semiconductor package designers who have the range to contribute across the full lifecycle of complex package and system development, and who enthusiastically seek full ownership of large scale, challenging designs from concept to production.
Roles and Responsibilities
Package planning and integration with die, package, and PCB design teams.
Package specification and analysis for high-speed serdes interfaces.
Bring up, testing, and characterization of high-speed serdes and memory interfaces.
Analysis of HBM and other advanced packaging technologies.
Specification and analysis of power and high-speed signaling requirements for high-speed networking systems across die, package, PCB, connectors, and cabling.
Work with systems engineers to define and realize thermal management solutions for high power networking devices.
Support operations team during package qualification and failure analysis.

Skills/Qualifications:
Hands on large body size, high power, high speed substrate design using Cadence APD/SIP
Strong understanding of SI/PI, and mastery of Ansys HFSS and SiWave.
Knowledge of package and PCB materials and material properties.
Experience with 2.5D packaging and interposer integration is a plus.
Proven track record driving substrate layout engineering teams.
Direct experience with production qualification and post-production activities.
MS or PhD in EE or MechE, plus 10+ years of experience

Target Companies: Cisco, Juniper, Google, Annapurna, Innovium, Mellanox/Nvidia, Broadcom, Barefoot, Intel, Fungible, Cavium/Xpliant, Marvell, Google, Cray, Mediatek/Nephos, Insieme, Nuova

Company Background
Enfabrica is on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, Enfabrica sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, Enfabrica is unleashing the revolution in next-gen computing fabrics.


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