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STA / FEINT Design Engineer
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Full-time
- Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded.
- Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology.
- PREFERRED EXPERIENCE: Experienced PD professional with industry experience in STA, constraints, timing signoff and physical design Expert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired).
- Good experience and understanding of DFT timing concepts, MBIST, Top level clock -implementation, Place and Route flows -floorplanning and placement, CTS and Route.
- Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
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