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Sr. Staff Design Engineer - Microarchitect
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- Configure Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
- Instruction fetch and decode, branch prediction Instruction scheduling and register renaming Out-of-order execution Integer and Floating-point execution Load/Store execution, prefetching Cache and memory subsystems Knowledge of Verilog and/or VHDL
- MS degree in Electrical or Computer Engineering with 5+ years or BS degree with 7+ years of practical experience
- Experience with Hardware multi-threading, virtualization, and SIMD designs
- MIPS offers comprehensive health, wellness, and financial benefits as partof a competitive total rewards package.
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