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SPE Analog Engineering
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$244,800 a year
Full-time
- The candidate will be part of Rambus Memory Interface Chips BU’s design group responsible for specifying, architecting, executing and productizing leading edge memory interface buffer chips for DDR5, DDR6 and beyond.
- Owner and domain expert of analog and mixed signal designs at chip and block level
- Supervise analog layout engineering to ensure attention to detail on high performance analog layout for critical IO blocks
- MSEE/Ph. D. with 10+ years of analog / mixed-signal circuit design experience
- Experience with Verilog coding is a strong plus
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