NXP Semiconductors

NXP's MCU/MPU Engineering (MME) team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for NXP's Automotive, Secure Edge, Advanced Analog and Radar Processing business lines.. Handling RTL Design for DFT related changes in both Subsystem level & Top level Designs.. Inserting of TAP, IOs, Test Pin multiplexing using internally developed and/or standard EDA DFT flows.. Driving Power Aware RTL/GLS simulation bring-up and setting up regression suite for both Non-ATPG & ATPG needs.. Well versed in Digital Design Concept, preferably having solid knowledge on Verilog/VHDL RTL coding.

technical lead

SoC Sr. DFT Technical Lead NXP's MCU/MPU Engineering (MME) team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for NXP's Automotive, Secure Edge, Advanced Analog and Radar Processing business lines. MME's SoC Hardware Architecture team produces architectural solutions covering the very wide range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low power devices to highly-integrated, high performance, multi-domain devices compliant with the latest automotive and industrial safety and security standards. Job Responsibilities:<ul><li>Handling RTL Design for DFT related changes in both Subsystem level & Top level Designs.</li><li>Inserting of Memory BIST and Repair logic for memories while driving its functional verification.</li><li>Analyzing Scan DRC reports and fixing DRC errors.</li><li>Analyzing ATPG reports on coverage and devise mechanism to improve coverage & generating patterns for ATE.</li><li>Experience with Siemen's Scan Streaming Network (SSN) highly desirable</li><li>Inserting of TAP, IOs, Test Pin multiplexing using internally developed and/or standard EDA DFT flows.</li><li>Driving Power Aware RTL/GLS simulation bring-up and setting up regression suite for both Non-ATPG & ATPG needs.</li><li>Bringing up Patterns on Wafer probe and on Final Test by working closely with Product & Test teams.</li></ul> Job Qualifications:<ul><li>DFT Lead with 10+ years of hands-on experience in DFT implementation and verification of scan architectures, JTAG, memory BIST, ATPG.</li><li>Leading experience of a team of 5+ team members.</li><li>Self-driven, results-oriented with a positive outlook, and a clear focus on high quality deliverables.</li><li>Good communicator and collaborator, able to see things from the other person's point of view.</li><li>Willing to take up new challenges in the project and a good team player.</li><li>Well versed in Digital Design Concept, preferably having solid knowledge on Verilog/VHDL RTL coding.</li><li>The candidate should have hands-on experience in the following areas:</li><li>Scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. </li><li>Debugging and root cause analysis of simulation and ATE failures.</li></ul>

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