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Senior Technical Lead
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- The Senior Hardware Engineer will be responsible for implementing functionalities such as DSP algorithms and communication protocols, high-speed interface protocols, and networking protocols in Field Programmable Gate Arrays (FPGAs).
- Responsibilities Rapidly develop concept to prototype, including digital, analog, and FPGA components.
- Develop all aspects of FPGA implementation, with emphasis on design partitioning, RTL synthesis and simulation, place and route, timing closure, IP integration, and system level debugging.
- Eight (8) years of experience with FPGA development in VHDL or Verilog as well as board-level design including FPGA selection, digital design, basic analog circuitry (filter/gain stages) including ADCs, DACs, switching voltage regulators, and platform bring-up.
- Hands on experience and a solid understanding in some or all of the following: common bus interfaces and IO's such as Gigabit Ethernet, JESD204, PCIe, USB, IC2, and JTAG. Hands on experience and a solid understanding in some or all of the following FPGA design tools: Altera (Intel) Quartus, Xilinx Vivado, Aldec Active-HDL or Riviera-PRO, Modelsim, and version control such as Subversion or git.
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