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Senior RTL Design Engineer (EInfochips Inc)
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$150,000 a year
Full-time
- 5+ years of experience applying digital design principles in SoC and/or IP development.
- Proficient in Verilog/System Verilog coding constructs.
- Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
- Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
- MUST HAVE design background in Arteris NoC (Network on Chip) RTL generation or based on any other NoC tool.
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