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Senior Lead DFT Design Engineer
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$138,600 - $257,400 a year
Full-time
- Looking for Lead SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT).
- Ability to lead from DFT Architecture to Silicon Debug is required.
- It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.
- Prior 15-20 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
- Should be able to lead DFT in projects from architecture to silicon debug
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