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RFIC - PLL Design Engineer
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$131,500 - $243,300 a year
- Key QualificationsTypically requires 3+ years of RF/analog and mixed-signal design experience in cutting-edge RF CMOS design.
- Direct experience in designing and bringing into mass production of wireless transceivers in deep sub-micron RFCMOS technology.
- Hands on experience in designing TDC, GRO, Digital Filters, Sigma Delta Modulators, Pre-scalers and MMD, DCOs, PFD-CP, and VCOs. Modeling, analysis and design of SD noise cancellation and spur cancellation techniques.
- Deep understanding of analog, mixed-signal and RF circuit design.
- Experienced in Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS) and similar tools.
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