Synopsys

Hands on experience in Circuit Design, Layout Design & spice simulations. Experience in standard cell circuits optimization to achieve better PPA.. Familiarity with layout design and experience in working with layout designers to optimize layout parasitic to achieve target PPA.. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors.. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package.

sr staff engineer

﻿Senior R & D Engineer (Standard Cell Library Design)48344BR USA - California - Mountain View/Sunnyvale Job Description and Requirements Senior R&D Engineer for our Logic Library Group in Sunnyvale, CA. We're looking for a Standard Cell Library Designer to join the team. Does this sound like a good role for you? Synopsys is hiring a Senior R&D Engineer for our Logic Library Group in Sunnyvale, CA. The ideal candidate will have extensive experience in the following areas: <ul><li>Bachelors or MSEE or equivalent from reputed universities </li><li>7 + years of Standard Cell library design experience. </li><li>Ability and willingness to do hands-on development as well as mentoring and coaching junior R&D engineers to expand their skills. </li><li>Ability to work effectively with geographically distributed R&D teams, and to engage in cross-functional collaborations for optimization across the entire design chain. </li><li>Effectively articulate ideas and requests to drive such collaborations. </li><li>Must have working experience on advanced technology nodes like 7nm, 6nm, 5nm, 4nm and 3nm </li><li>Hands on experience in Circuit Design, Layout Design & spice simulations </li><li>Experience in designing flips flops, clock gating cells, level shifters, power gating cells and other complex circuits. </li><li>Clear understanding of CMOS device characteristics and design rules in submicron process nodes. </li><li>Knowledge of submicron process issues, especially in FINFET technologies</li><li>Familiarity in running high sigma variation analysis in smaller technology nodes </li><li>Experience in standard cell circuits optimization to achieve better PPA. </li><li>Familiarity with layout design and experience in working with layout designers to optimize layout parasitic to achieve target PPA. </li><li>Involvement in layout extraction and understanding of layout dependent parameters in the extracted netlist. </li><li>Understanding of timing/leakage characterization of Standard cells </li><li>Scripting capability in TCL/PERL/Python. </li><li>Strong Analytical and Logical skills. </li></ul>At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.The base salary range across the U.S. for this role is between $155,000-$233,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.Job Category Engineering Country United States Job Subcategory R&D Engineering Hire Type Employee Base Salary Range $155,000 - $233,000

START NEW SEARCH