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Principal Verification Engineer I
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- JOB DUTIES AND RESPONSIBILITIES Lead the evaluation and technical implementation of FPGA and digital design simulation, verification and emulation infrastructure.
- Develop state-of-the-art UVMf-based top-level and module-level testbenches using block-to-top best practices for reusability, including both control and data plane stimulation using VIP & System Verilog DPI-C integration with existing MATLAB and Python numerical models.
- Work closely with the engineering and senior leadership teams to train and mentor engineers at all experience levels on UVMf testbench usage and modern approaches to FPGA/digital design.
- Work with the modeling and scientific staff to implement DPI-C dataplane verification interfaces into existing MATLAB and Python models.
- Continually evaluate current processes regarding FPGA and digital design with a focus on Xilinx TLM models and QEMU-RP integration.
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