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Power Management Design Engineer
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$134,500 - $201,500 a year
Full-time
- Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains and multiple power domains
- Experience in low power design methodology and clock domain crossing designs
- Understanding of full RTL to GDS flow to interact with DFT and PD teams
- Digital design and development (RTL) working in close collaboration with Multi-site leads across US and India
- Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed.
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