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Mixed - Signal Verification Engineer
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- In this role, you will be verifying RF/Mixed-Signal blocks and SOCs using SystemVerilog to create testbenches, checkers, models and tests.
- Industry verification experience with RF/Mixed-Signal blocks and SOCs.
- Expertise building Mixed-Signal testbenches, checkers and tests using System Verilog.
- Expertise creating and using real-numbered analog behavioral models in System Verilog/Verilog-AMS.
- Experience in HVL methodology (UVM/OVM/VMM) and HDL (System Verilog, Verilog) for verification.
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