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IC Packaging Engineer
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$106,800 - $178,000 a year
Full-time
- for latest silicon nodes on chip floorplan & bump patterns design and optimization for package design requirements (e.g. substrate/package structure, BGA pattern development, s-parameter understanding and optimization [RL, NEXT/FEXT, IL etc.
- Work with marketing and IC design teams to select the optimum package solution on cost, performance, manufacturability, and reliability
- Work with IC design, system design, package SI/PI & thermal engineering teams to design custom packages using Cadence APD
- Create package design documentation and assembly instructions
- Strong authority on Cadence APD for custom substrate design
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