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Design Integration Engineer
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- All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
- As a Design Integration Engineer, you will be involved with all phases of implementing high performance, low power wireless SoCs from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: - Generate chip or block level static timing constraints.
- Synthesize design with UPF/DFT/BIST. - Close timing on critical blocks by working with design and PD teams.
- Knowledge of the ASIC design flow, synthesis, static timing analysis, scripting, and netlist generation.
- Understanding of UPF and low-power design & implementation techniques.
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