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Design Engineer for Test
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$123,419 - $185,123 a year
Full-time
- You will work on the design, RTL, and RTL/GLS validation, in the following DFT domains: TAP Controller, Scan/ATPG, Array DFT (MBIST).
- You will also contribute or be involved with trace pattern generation efforts as well as post-silicon enabling debug support and/or analysis of the DFT features and content types you are responsible for.
- Bachelor's degree in electrical/computer engineering or related STEM degree with 7+ years of industry experience in at least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST)
- EDA vendor-supported scan architectures and tools, covering synthesis, timing, DRC, ATPG, GLS (Unit delay and Timing/SDF based), and tester bring up preferably Mentor/Siemens Tessent Shell, TestKompress, ATPG coverage debug
- EDA tools such as ATPG tools, Siemens Tessent Shell, Synopsis VCS simulation and/or debug tools
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