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Analog Design Engineer - PDK Support
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Full-time
- This role is to support PDK for custom template design layout/integration validation, and for analog design impact analysis and design across all Intel leading edge PDKs. You will also lead integration layout validation of custom template library cells like MFC(Multi-Finger-Capacitor), BGdiode, resistor, or clamp to make sure integration guidelines to foundry customers are all clear and correct.
- For impact analysis, you'll collaborate with DE teams to outline industry standard analog FOM and relevant indicators, construct, maintain and generate the simulation results, and using your deep understanding of analog design behind each indicator to interpret the gap between PDK to PDK and conducting analysis across all Intel leading advanced technology process nodes to support relevant documentation.
- Candidate must possess a BS degree with 4+ years of experience or MS degree 3+ years of experience or PhD degree with 1+ years of experience in Electrical/Computer Engineering, or related STEM fields.
- Prior design ownership for analog IPs (for example, PLL, AADC, ADAC, PCIE, GPIO, DDR) or equivalent designs, and knowledge for foundation circuits/blocks for these IPs.
- Proficient in performing spice simulation, or hspice, or spectre, or equivalent simulators to extract simulation results.
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