SRAM Development Engineer

Job Title:SRAM Development Engineer (Roadmap & DTCO) – 2 nm Technology Node and beyondTeam: Enablement / Memory DevelopmentLocation: Albany (NY)--preferred, Santa Clara (CA), or Tokyo (Japan)OverviewRapidus Corporation is developing next-generation semiconductor technologies at the 2 nm node and beyond.We are seeking talented engineers to join our SRAM Development Team, responsible for SRAM bitcell, peripheral circuit, macro, and compiler development, as well as SRAM technology roadmap planning and DTCO (Device-Technology Co-Optimization).This role offers the opportunity to work on cutting-edge memory architectures while collaborating closely with process, device, DTCO, and design enablement teams to define scalable SRAM solutions for future technology nodes.Key ResponsibilitiesDesign and develop SRAM bitcells, peripheral circuits, SRAM macros, and compilers for advanced technology nodes (2 nm and beyond).Perform transistor-level circuit design and simulation to meet performance, power, stability, and variability requirements.Collaborate with process integration and device teams to improve SRAM cell robustness, yield, and manufacturability through DTCO activities.Define and maintain the SRAM technology roadmap, including scaling strategy, bitcell architecture evolution, and feature planning for future nodes.Lead and contribute to DTCO studies for SRAM, evaluating device options, layout constructs, Vt choices, and PPA trade-offs.Work closely with standard cell, GPIO, and logic IP teams to ensure cross-IP alignment and consistent design assumptions.Participate in SRAM macro architecture definition and compiler feature planning (timing, redundancy, power management).Conduct layout verification, DRC/LVS debug, parasitic extraction, and variation analysis for SRAM arrays and peripherals.Analyze silicon test and characterization data and support failure analysis and yield improvement activities.Work with EDA vendors and PDK teams to define and validate SRAM modeling, sign-off, and enablement flows.Contribute to SRAM qualification test chips and shuttle programs.Required QualificationsB.S. or M.S. in Electrical Engineering, Electronics, or related field.3+ years of experience in SRAM circuit design, memory architecture, or advanced CMOS memory development.Strong knowledge of SRAM bitcell design, peripheral circuits, and variability-aware design techniques.Experience with EDA tools for schematic design, layout, and simulation (e.g., Cadence Virtuoso, Synopsys HSPICE, Siemens Calibre).Solid understanding of device physics, PVT variation, and reliability challenges at advanced nodes.Ability to work effectively with cross-functional teams (process, DTCO, EDA, test, and enablement).Strong communication and technical documentation skills in English.Preferred QualificationsExperience with FinFET or nanosheet (GAA) SRAM design.Experience contributing to SRAM technology roadmap definition or long-term memory scaling strategy.Familiarity with DTCO methodologies, including device/layout co-optimization and trade-off analysis.Experience with SRAM compiler development and automation flows.Hands-on experience with silicon debug, failure analysis, and test-chip bring-up.Knowledge of EDA PDK development or SRAM model validation flows.Business-level Japanese proficiency is a plus.