Digital Verification Engineer

Digital Verification EngineerResponsibilities:Develop test plans and verification infrastructure for low-power ASIC designsBuild verification environments using SV/UVM methodologyBuild reusable bus functional models, drivers, monitors, checkers and scoreboardsDebug/triage automated regressions, run gate level simulations, and perform coverage analysisRequirements:Proficiency in verification test planning, test bench architecture, assertions, problem solving and debuggingConstrained random verification experience with System Verilog using OVM or UVMSet up coverage driven verification (code/functional/assertion coverage)Strong knowledge of Verilog or VHDLBS or MS (preferred) degree in EE or equivalent, with 5+ years of experienceNice to Have:Experience in testbenches (block, system) and setting up verification flow from ground-upUnderstands secure/non-secure, interrupts, memory, and clock frequency switchingFamiliar with low-power designs, understands power saving techniques and verificationsWireless communications, knowledge of BLE at the protocol levelLocation:Campbell (Silicon Valley), California, USAIrvine, California, USA