ASIC Physical Design & Layout Engineer (FinFET)

Company DescriptionSARACA is a global engineering R&D services company serving 25+ Fortune 500 customers across industries such as MedTech, Aerospace, Automotive, Semiconductor, and Defense. With its ISO 13485 certification, SARACA specializes in advanced design, development, and compliance for medical devices and other high-tech systems. Backed by a team of 400+ engineers and management consultants, the company delivers cutting-edge product engineering solutions globally. SARACA is committed to fostering a thriving work environment of innovation and learning, driving business success for clients worldwide. The company proudly upholds a strong culture of diversity, equity, and inclusion.Role OverviewWe are seeking an experienced engineer with strong expertise in analog/mixed-signal layout design for deep submicron CMOS technologies, including advanced nodes (FinFET). This role focuses on delivering high-quality, optimized layouts while influencing design methodologies, CAD flows, and signoff strategies. Key ResponsibilitiesDrive improvements in tools, flows, and design methodologies using a data-driven approach Perform layout design and optimization for analog/mixed-signal circuits meeting area, power, and performance goals Execute block-level and full-chip integration Support signoff closure including timing (SI/OCV), power, IR drop, and physical verification Analyze and resolve DRC, LVS, ERC issues efficiently Apply signal integrity (SI) mitigation and timing optimization techniques Collaborate across teams to ensure design robustness and successful tape-out  Required Skills8+ years of experience in analog/mixed-signal layout design 3+ years of experience with advanced nodes (FinFET technologies) Strong knowledge of ASIC/SoC CAD flows and methodologies Hands-on experience with physical verification (DRC/LVS/PEX/ERC) and EM/IR analysis Proficiency in EDA tools: Synopsys (ICC/ICC2), Cadence (Innovus, Virtuoso) Strong programming skills in Perl, TCL, and Python Solid understanding of device physics, SPICE simulations, and Verilog netlists Experience working in UNIX/Linux environments Excellent analytical, communication, and problem-solving skills  Preferred SkillsExperience in design automation and scripting Strong understanding of timing closure, SI, and power optimization techniques.