DFX Verification Engineer
Role: DFX Verification Engineer
Location: Bay Area, CA, Santa Clara, CA (Onsite)
Experience: 4+ yearsRead all the information about this opportunity carefully, then use the application button below to send your CV and application.Key Responsibilities
Develop and execute verification plans for DFx features including:
Scan (stuck-at, transition fault)
MBIST / LBIST
Boundary Scan (JTAG)
Memory repair and redundancy
Low-power test scenarios
Create and maintain testbenches usingSystemVerilog/UVMfor DFx validation
Verify:
Scan chain integrity and connectivity
Test mode functionality and coverage
ATPG pattern validation and debug
BIST controllers and memory test logic
Technical Skills
Strong knowledge of:
DFT concepts (Scan, ATPG, MBIST, JTAG)
Digital design fundamentals
xywuqvpExpertise in:
SystemVerilog and UVM
Simulation tools (VCS, Xcelium, Questa)
Familiarity with:
ATPG tools (TetraMAX, Modus, FastScan)
Debug tools (Verdi, DVE)
Understanding of:
Low-power design (UPF/CPF)
Clocking and reset strategies