FPGA Design Engineer (Active Secret Clearance required)

Location: Reston VA and Camden NJ, fully onsite (No relocation assistance)Number of openings: 2-4Benefits: None/ContractStart Date: 2 weeks after offerClearance Level: Active SecretSchedule: 9/80 (80 hours over 9 days with every other Friday off)Must- Haves (Hard Skills):Experience with Xilinx FPGAs and VivadoExperience with Revision control system4-6 years of minimum experience with VHDL experienceExtensive FPGA design going through design and verification processEthernet framing and protocol experience in FPGA (Primarily working on the Ethernet side but if they can demonstrate the PCIe that would suffice) – Looking for the actual interface experience than just the algoritmsNice -To- Haves:Experience with mapping algorithms to architectureExperience in C++ (OOP)Experience with any of protocols : Ethernet, TCP/IP, PCIe, NVMe, USBExperience with Xilinx SoC design with SDKs and PetaLinux OSExperience with High-Level Synthesis (HLS) with Vivado HLX or Mentor CatapultExperience with Earned Value Management (EVM) – understanding of the schedule, scope, time etc. from an Agile environmentMust- Haves (Soft Skills)Good written, verbal, and presentation skillsStrong leader, able to lead design teamsActive Secret Clearance requiredDegree/Certification RequirementsBachelor of Science (BS) -Four year degree or Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science)J-18808-Ljbffr