DFT Intern (12 Week Internship)

Requirements You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field Familiarity with a hardware description language (Verilog or SystemVerilog) Exposure to ASIC or SoC design concepts Familiarity with digital logic design fundamentals Familiarity with standard ASIC design flow steps (synthesis, STA, DFT) Familiarity with scripting in Python, Tcl, or another language Are able to learn quickly about transformers and other aspects of modern artificial intelligence (Desirable) Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression (Desirable) Experience with Tessent or similar DFT tooling (Desirable) Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF) (Desirable) Exposure to DFT flow automation or regression infrastructure (Desirable) Familiarity with clocking and reset schemes We encourage you to apply even if you do not believe you meet every single qualification What the job involves As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed We are looking for Summer ’26, Fall ’26, Spring ’27, and Summer ’27 interns 12‑week paid internship #J-18808-Ljbffr