RTL Integration Engineer

We are looking for an experienced RTL Integration Engineer to join our ASIC/SoC design team. The successful candidate will be responsible for integrating RTL blocks, subsystems, and IP into top-level designs, ensuring functional correctness, performance optimization, and seamless handoff to verification and physical design teams. Key Responsibilities Own and execute RTL integration of IPs and subsystems into the SoC top-level. Develop and maintain top-level RTL, interconnect, and clock/reset integration logic. Ensure design meets functional, power, performance, and area (PPA) targets. Collaborate with front-end and back-end teams to close on timing, lint, CDC, RDC, and synthesis requirements. Drive integration best practices including hierarchy definition, naming conventions, and signal integrity. Debug and resolve integration-related functional and structural issues. Generate and maintain design collaterals (netlists, constraints, scripts, documentation). Work with verification teams to enable testbenches, simulations, and regression infrastructure for SoC-level validation. Support emulation/FPGA bring-up and silicon validation teams for integration-related debug. #J-18808-Ljbffr