Silicon Validation Engineer 4

IntroductionThis role involves developing and maintaining automated metric collection from FPGA implementation flows, enabling repeatable analysis of build quality, timing, and infrastructure health.Job Title: Silicon Validation Engineer 4 Location: Remote ( PST Preferred ) Salary Range: $85/hr to $90/hr on W2Required Skills & QualificationsStrong experience with TCL scripting for VivadoProficiency in PythonSolid understanding of FPGA implementation flows, timing, and utilizationPrior work experience at client or in client's IndustryFamiliarity with CI/CD-driven FPGA buildsPreferred Skills & QualificationsExperience with TCL scripting for QuartusFamiliarity with CI/CD-driven FPGA buildsExperience working with large or production FPGA infrastructuresDay-to-Day ResponsibilitiesDevelop scripts to extract metrics from Vivado implementation runsAutomate collection of timing, utilization, and quality metrics using TCL and PythonIntegrate extracted metrics into existing data pipelines and toolingSupport and modify FPGA constraint and automation scripts as neededCollaborate with internal and partner teams to enable reliable metric generationExtend metric collection to additional FPGA platforms or legacy flows as requiredCompany Benefits & CultureCompetitive salary and comprehensive benefits packageOpportunities for professional growth and developmentInclusive and dynamic work environmentFor immediate consideration please click APPLY to begin the screening process with Alex.