Senior Design Engineer

We strive to be Your FutureYour Solution to accelerate your career! Contact Hannah Wilson at hwilson@saigepartners.com, you can also schedule an appointment at to learn more about this opportunity!Position: Senior RTL Design Engineer (Folsom, CA) Job Overview:We are seeking an experienced Senior RTL Design Engineer to lead the design and implementation of advanced FPGA-based solutions. This role will focus on architecture development, high-speed interface design, and RTL implementation for complex systems. The ideal candidate will collaborate with cross-functional teams to drive designs from architectural concept through FPGA validation and silicon verification while optimizing performance, power, and area.This is a contract role and is not eligible for C2C or W2 referral candidates. What you will be doing as a Senior RTL Design Engineer…• Participate in defining system architecture and microarchitecture for complex FPGA-based designs.• Develop prototypes, simulate models, and define system-level requirements and specifications.• Architect and implement multi-FPGA partitioning solutions for scalable hardware systems.• Design, implement, and debug high-speed interfaces, including Ethernet, PCIe, and DDR.• Apply RTL design and implementation techniques to meet power, performance, and area (PPA) goals in collaboration with physical implementation teams.• Develop and release FPGA designs through the full development lifecycle including:o Microarchitecture definitiono RTL design and implementationo Physical implementationo Timing closureo Simulation and validationo Lab-based silicon validation• Perform design trade-off analysis to optimize cost, size, power consumption, performance, and feature sets.• Collaborate with cross-functional teams including architecture, verification, and hardware validation groups. Skills you ideally bring to the table as a Senior RTL Design Engineer…• Bachelor's degree in Computer Engineering, Electrical Engineering, or Computer Science (Master's or PhD preferred).• 10+ years of experience in architecture development and FPGA design.• Strong experience with FPGA HDL development, simulation, and analysis.• Proficiency in VHDL and/or Verilog for RTL design.• Experience performing static timing analysis and timing closure for high-performance FPGA designs.• Experience with RoCEv2 (RDMA over Converged Ethernet) including:o RDMA READ/WRITE operationso Queue Pair (QP) managemento Congestion control• Experience developing NVMe over Fabrics RTL, enabling direct data transfer between host memory and storage targets.• Experience tuning and integrating high-speed interfaces, including:o PCIe Gen4/5/6o 100G / 200G / 400G Ethernet MAC/PCS• Demonstrated ability to work effectively in a collaborative engineering environment.Learn more about Saige Partners on Facebook or LinkedInSaige Partners, one of the fastest growing technology and talent companies in the Midwest, believes in people with a passion to help them succeed. We are in the business of helping professionals BuildCareers, Not Jobs. Saige Partners believes employees are the most valuable asset to building a thriving and successful company culture, which is why we offer a benefit package and convenient weekly payment solutions that helps our employees stay healthy and maintain a positive work/life balance. Contact us to learn more about the opportunity below or check out other opportunities at https://careers.saigepartners.com/.