Backend EDA Compiler Engineer

Partcl is ending the hardware lottery.We are developing the next generation of chip design automation tools with a focus on performance, scalability and productivity. We envision a future where hardware engineers benefit from advances in AI and believe the first place to start is with advanced optimization tools.We’re looking for engineers who think in terms of intermediate representations and passes — people who can design the data models that physical-design tools run on, not just use them. You should be able to move seamlessly between high-level IR design and low-level performance work, building the infrastructure that lets placement, routing, and timing engines operate at massive scale.At Partcl, we’re not here to play it safe - we’re here to win. We want people who wake up every day wanting to win too. If you are interested in solving massive-scale problems in physical AI, come join us.What You Will DoDesign the core intermediate representations that physical-design tools use to reason about chipsBuild compiler-like pipelines that lower, normalize, and transform design data across stages (netlist → floorplan → PnR → sign-off)Architect the physical-design data model as a first-class IR, not just a storage formatCreate high-performance loaders, serializers, and transformation passes for LEF/DEF, Liberty, SPEF, GDSDevelop APIs that make analysis and optimization passes fast to write and reason aboutOwn correctness invariants: name resolution, scoping, units, coordinate systems, legalizations, constraintsOptimize for query latency, cache locality, memory layout, and parallel traversalBuild validation and rewriting passes that catch inconsistencies and automatically repair design dataWork directly with PnR, STA, and optimization engineers to co-design new IR features and passesTreat the database as a compiler backend, not a dumping groundRequirementsStrong background in compilers or IR design (LLVM, MLIR, TVM, CIRCT, or equivalent experience)Proficiency in Rust for low-level systems work; Python for tooling and pipelinesExperience designing data structures for large graphs / sparse relations / geometric dataUnderstanding of incremental computation, dependency tracking, and versioning of IR statesAbility to reason about correctness, determinism, and reproducibility in complex toolchainsComfortable digging into massive designs and fixing pathological corner casesNice To HaveExperience with CIRCT/MLIR or custom EDA IRsPrior work on static analysis, transformation passes, or compiler runtimesFluency with physical-design file formats: LEF/DEF, Liberty, SDC, SPEF, GDSDeep familiarity with chip backend concepts: floorplanning, placement, routing, CTS, extractionKnowledge of timing models (CCS/LVF) and constraint propagationExperience with columnar or in-memory formats (Apache Arrow, Parquet, custom SOA layouts)Parallel compiler / GPU acceleration experience