IP Characterization engineer

Job Title: Senior Standard Cell & IP Characterization Engineer

Experience: 6+ Years

Location: Austin, TX

Job Type: 6+ months contract

Education: Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related technical field

Job Overview: We are looking for an experienced Senior Standard Cell & IP Characterization Engineer with strong expertise in semiconductor library characterization, foundation IP development, transistor-level simulations, and design kit generation. The ideal candidate will have hands-on experience working with high-performance, low-power, and ultra-high-density standard cell libraries, memory compilers, and hard IPs. This role involves executing characterization flows, generating front-end and back-end design kit views, conducting high-sigma statistical analysis, and ensuring the quality and completeness of library releases. The candidate will collaborate closely with Physical Design (PD), RTL, and Backend CAD teams to resolve design kit quality issues, drive PPA improvements, and support program milestones. Candidates should bring strong proficiency in Cadence Virtuoso, HSPICE, Spectre, SPICE simulations, and scripting languages such as Python, TCL, Perl, or SKILL.Key Responsibilities1. Standard Cell and IP Characterization

• Execute characterization flows for high-performance, low-power, and ultra-high-density standard cell libraries and hard IPs.
• Perform transistor-level simulations using SPICE-based simulation environments.
• Develop, execute, and maintain automated library characterization flows.
• Perform characterization of standard cells, memory compilers, and other foundation IPs.
• Ensure the completeness, accuracy, and quality of design kits and associated library views.
• Generate front-end and back-end design kit views for release.2. Transistor-Level Simulation and Circuit Analysis
• Perform transistor-level circuit simulations and analysis using tools such as HSPICE, Spectre, and Cadence Virtuoso.
• Execute high-sigma Monte Carlo simulations using PrimeSim DR and High Sigma Analysis (HSA).
• Conduct statistical analysis to evaluate design robustness, variability, and performance across process, voltage, and temperature (PVT) conditions.
• Perform direct custom physical layout activities and support circuit-level optimization.
• Utilize PrimeSimDR/HSMC for advanced simulation and characterization activities.3. Library Qualification and Design Kit Validation
• Perform library quality assurance and qualification using Crosscheck and SolidoChar.
• Validate library characterization results and ensure consistency across design kit releases.
• Work with EDA validation tools such as LEC, Calibre, Totem, PrimeLib, and SolidoIPValidation.
• Identify, debug, and resolve design kit quality issues in collaboration with cross-functional engineering teams.
• Ensure front-end and back-end design kit views meet release requirements.4. PPA Analysis and Foundry Benchmarking
• Drive Power, Performance, and Area (PPA) analysis and engineering benchmarking activities within a foundry environment.
• Evaluate library and IP performance across different technology nodes and design conditions.
• Support PPA optimization through characterization, circuit analysis, and design validation.
• Collaborate with Physical Design, RTL, and Backend CAD teams to address design quality issues and achieve program milestones.5. Test Chip Design and Tapeout
• Participate in test chip planning, implementation, and tapeout activities.
• Own end-to-end design, implementation, and sign-off of assigned partitions on test chips.
• Apply knowledge of synthesis, Place and Route (PnR), Static Timing Analysis (STA), and Physical Design Verification (PDV) tools.
• Support block-level design convergence and sign-off activities.
• Ensure design partitions meet performance, physical design, and sign-off requirements.6. Automation and Scripting
• Develop and maintain automation scripts for large-scale characterization, evaluation, and data analysis pipelines.
• Use Python, TCL, Perl, or SKILL to automate engineering workflows and improve characterization efficiency.
• Analyze simulation and characterization results to identify performance trends, design issues, and optimization opportunities. Required Technical Skills
• 6+ years of experience in semiconductor engineering, preferably within a foundry environment.
• Strong experience in standard cell library characterization and foundation IP characterization.
• Hands-on experience with characterization flows for standard cells, memory compilers, and hard IPs.
• Strong understanding of front-end and back-end design kit generation and release requirements.
• Expert-level proficiency in Cadence Virtuoso, HSPICE, and Spectre.
• Hands-on experience with transistor-level SPICE simulations.
• Experience with library characterization tools such as Liberate and Totem.
• Experience with PrimeSim DR and High Sigma Analysis (HSA).
• Proficiency in Python, TCL, Perl, or SKILL scripting.
• Experience with high-sigma Monte Carlo simulations and statistical analysis.
• Experience with Crosscheck and SolidoChar library QA and qualification checks.
• Working knowledge of synthesis, Place and Route (PnR), STA, and Physical Design Verification (PDV).
• Proven participation in semiconductor test chip tapeouts, including ownership of design and sign-off of individual partitions.