Senior ASIC Engineer

Job Title: Senior ASIC Engineer Location: Pleasanton, CA (Onsite) Duration: 12+ Months Role Work involves executing complete verification project in the role of project leader with hands on experience, mentoring, client communication / interactions, in-depth technical reviews and close tracking of technical as well as management aspects. A great team player and motivator. Very much adaptive to demanding situation and fast decision maker. Must have experience in 5+ team size handling as a Technical Lead in 1+ Project Technical Experience: At-least 3+ years of experience in System Verilog HVL. At-least 2+ year of experience in UVM. Must have executed at-least few SoC Verification projects 2+ Must have Netlist (GLS) setup & extensive debug with Timing (SDF) simulations experience 1+ Year of Low-Power & UPF flow Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions and coverage closure. Knowledge of at-least one industry standard protocols like Ethernet, MIPI, ARM Processors, AXI/AHB. Make/Perl/Python Management Define/derive Scope, Estimation, Schedule and Deliverables of proposed work. Assure compatibility of resources, tools, platform Work with customers through acceptance of deliverables. Effectively manage team members through coaching and mentoring and provide guidance and career planning to team-members. Ensure customer satisfaction. Soft Skills: Communication [Written + Oral] Attitude Problem solving + Decision Making Team Player + Leadership quality+ Ownership Flexibl Job Type: Contract Benefits: Employee discount Life insurance Referral program Schedule: 8 hour shift Work Location: In person