Machine Learning Systems Intern
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Hybrid SSM‑Transformer models have a unique advantage for on‑chip memory efficiency:SSM layers compress sequence history into a fixed‑size recurrent stateAttention layers store key‑value caches that grow with context lengthThis leads to an important design question: For a given model configuration and maximum context length, can on‑chip SRAM be sized so that inference runs entirely on chip—eliminating the need for slower off‑chip HBM or DRAM?What the intern will work on:The intern will model and analyze memory behavior during inference of hybrid SSM‑Transformer models, with a focus on avoiding off‑chip memory accesses. Key responsibilities include:Modeling data movement between SRAM and HBM/DRAM during inferenceSweeping parameters such as:SRAM capacityContext lengthModel dimensionsMapping the feasibility boundary where inference can be performed fully on chipBreaking down per‑layer memory working setsIdentifying when and why memory spills occurExploring tiling and scheduling strategies to extend the no‑spill regionValidating analytical results through simulation