Senior Principal Verification Engineer - DDR/UVM Expert

A global semiconductor company is seeking a Senior Principal Verification Engineer to define and execute verification plans for DDR memory interface products. This Full-Time position offers a hybrid work environment, with an emphasis on collaboration and mentoring junior engineers. Qualified candidates will have significant experience in System Verilog, a strong background in verification, and good communication skills. A competitive compensation package is included, reflecting our commitment to innovation, inclusion, and teamwork. J-18808-Ljbffr