RISC-V Verification Engineer - Python & ISA Tooling

Qualcomm is seeking a CPU-design verification engineer to contribute to a Python-based random test generation framework and its assembler library, powering a RISC-V ISA verification toolchain. You will help drive a JIT-style generator producing ELF binaries for the RVA23.1 ISA, including privileged modes, virtual memory, and interrupts. You will work with ISS and RTL teams to triage failures, craft regression scenarios, and refine constraint logic across register allocation and address-space