Senior Foundry Engineer, Silicon Technology

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Job DescriptionWe are seeking a Senior Foundry Engineer, Silicon Technology to support foundry engagement, silicon-to-model correlation, tapeout readiness, and yield improvement for advanced semiconductor products. This person will work closely with internal design, CAD layout, product engineering, test, reliability, operations teams and external foundry partners to identify risks, assess product impact, and drive timely resolution of process, PDK, model, DRC/DFM, and silicon-related issues.Responsibilities IncludeSilicon, process and yield correlationAnalyze process inline data, silicon test data, process drift and process correlation data Fine tune processes to optimize power, performance and yieldHelp identify process related contributors to parametric drift, yield loss, leakage, reliability riskWork with foundry and internal teams to investigate yield issues and process excursionsPerform layout analysis where needed to understand process sensitivity, failuresTapeout and DFM supportSupport product tapeouts, tapeout readiness reviews from a PDK, DRC/DFM, device model and reliability perspectiveRun or coordinate DFM checks on products and summarize findings for design and layout teamsCoordinate between foundry and physical design teams to disposition waivers taking performance, leakage, manufacturability and reliability in mindDocument known PDK, model, DRC, DFM or process risks before tapeoutMaintain an internal PDK qualification database across foundries and process nodes to reduce tapeout risk from unnoticed PDK or model changesFoundry and PDK supportSupport technical interactions with foundry partners on PDK, device models, process assumptions, design rules, DRC/DFM decks and reliability collateralTrack PDK versions, model updates, DRC/DFM runset changes, and foundry signoff recommendationsCompare PDK changes across versions and summarize potential design, layout, model or signoff impactDevice model and circuit model evaluationValidate model behavior across voltage bias, temperature, process corners, and relevant operating conditionsCompare silicon measurements against SPICE/model predictions and help identify model gapsBasic QualificationsB.S or M.S in Electrical Engineering, Material science, Semiconductor engineering or a related technical field5+ years of experience in semiconductor device engineering, foundry interface, silicon technology, process integration, yield/process correlationRequired ExperienceWorking knowledge of semiconductor process flows, device physics, manufacturability, reliability and yield driversExperience supporting tapeouts, PDK validation, models, DRC/DFM, silicon bring upExperience analyzing silicon, wafer-level, process monitors, product test, characterization, or reliability dataPrior experience at a foundry, IDM, fabless semiconductor company or a PDK/enablement organizationFamiliarity with SPICE models, process corners, device behavior, layout effects and silicon-to-model correlationAbility to communicate technical issues clearly across design, CAD, layout, test, products engineering and external foundriesFamiliarity with using TSMC as a foundryPreferred ExperienceExperience with advanced FinFET, gate-all-around/nanosheet technologies and BiCMOS technologiesExperience with SRAM, analog/mixed signal, RF, Serdes, low power design constraintsExperience benchmarking foundry nodes using spice models on representative circuitsExperience using foundry models to simulate junction breakdowns, SOA, ESD, aging, reliability or device operating limits We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.