6B1DI4-Elect Design and Analy Engr 4 - 64Y-Microelectronics

ResponsibilitiesWrite SystemVerilog/UVM testbenches to verify ASICs and FPGAs.Develop self-checking, reusable UVM components: drivers, monitors, scoreboards, sequencers.Build functional coverage models and close code coverage gaps.Create tests that verify DSP and third-party IP integration.Run simulations, linting, CDC checks, static timing checks, and gate-level regressions.Use scripting (Python/Perl/Make) and revision control (git/svn) to automate flows.Support FPGA bring-up, hardware emulation/prototyping, and hardware integration tests.Collaborate with system and hardware teams to capture requirements and debug issues.Required SkillsBachelor's degree in EE, CE, CS, or related field (or equivalent experience).Experience with ASIC/FPGA verification using SystemVerilog and UVM.Ability to build self-checking testbenches and use object-oriented SV features.Familiarity with functional coverage and code coverage closure.Comfortable in Linux and using scripting tools.Preferred Skills2+ years (Associate) or 5+ years (Experienced) verification experience.Experience with hardware emulators (e.g., Palladium) and FPGA prototyping.Knowledge of high-speed SerDes (PCIe, Ethernet, JESD204C).Experience with SVA (SystemVerilog Assertions) and RTL-to-GDS flows.Familiar with space/radiation mitigation techniques is a plus.J-18808-Ljbffr